The invention relates to a sequencer and interface for a neural network, and specifically to a sequencer and interface which is operable to effect the transfer of data and control instructions to an array of processor nodes in a single-instruction stream/multiple-data stream processor.
Some form of sequencer is present in every computer system. However, in parallel systems, and particularly in neural network single-instruction stream/multiple-data stream (SIMD) systems, known to those skilled in the art, the sequencer is operable to control the input of commands to the processing portion of the computer only. In those instances where a sequencer does transmit both instructions and data, the instructions and data are not capable of simultaneous transmission to the processor portion of the computer. Additionally, known parallel processing sequencers provide only uni-directional parallel data communications between a processor portion of a computer and the sequencer and do nothing to synchronize the external and internal data flow to/from the processor.
A limitation of known sequencers is that a data stream must be manipulated as a whole. This can be particularly time consuming in the event that a particular portion of the data stream is required for manipulation by the processor portion of the computer.
An object of the invention is to provide a sequencer which is capable of providing control instructions and bi-directional parallel data communication between the sequencer and an array of processor nodes.
Another object of the invention is to provide a sequencer which provides for direct routing of processor array output back into the processor array for further processing.
A further object of the invention is to provide a sequencer which provides for direct routing of data to/from another sequencer.
Another object of the invention is to provide a sequencer which provides for direct routing of data from a processor array, through a sequencer, and to/from a data using/generating device.
Still another object of the invention is to provide a sequencer which synchronizes asynchronous, external data flow, to a synchronous, internal data flow in a neural network processor node array.
Yet another object of the invention is to provide a sequencer which provides multiple I/O virtual channels for data flow.
Another object of the invention is to provide a pointer manipulation mechanism in a SIMD neural network architecture.
A further object of the invention is to provide a sequencer which has the ability to manipulate a data stream to direct a particular point of the data steam to the processor array for processing.
Yet another object of the invention is to provide a sequencer which provides computation of an address in a control processor to transfer data from the control processor to a processor node.